1. Field of the Invention
The present invention minimizes transient noise during the switching operation of output buffers by employing a novel method and apparatus for controlling the slew rate of the output buffer data transitions.
2. Description of the Related Art
When integrated circuits are required to drive high capacitive loads with output buffers designed to switch at high frequencies, for example above 100 MHz, high transient currents are generated creating power supply and ground bus noise. This can cause deleterious effects to adjacent circuits in the system.
An integrated circuit (IC) includes bonding pads to which thin bond wires are attached to connect the IC to the IC package lead frame, which in turn is connected to a printed circuit board. The leads of the package lead frame have a certain amount of inductance, as do the bond wires. These inductances have a cumulative effect in generating noise on the power and ground supplies as the speed of integrated circuits increase, which can be understood with reference to the circuit model of FIG. 1.
To meet higher system performance it is desirable to have high speed output buffer circuits driving large capacitive loads. However, the faster switching rate causes an increase in the rate of change of current which in turn generates a higher voltage drop across the inductors. The voltage drop across an inductance is equal to the inductance multiplied by the rate of change of current. This is expressed as L * di/dt, where L is the value of the inductance and di/dt is the rate of the change of current. Hence, the larger the di/dt (i.e., the faster the switching speed) for a given value of inductance, the larger the voltage drop across the inductor.
The output load must be charged and discharged at high speeds. The discharge of the output path occurs rapidly and large current flows through the inductance. Typically, the output current sinking capability required for a given MOSFET output buffer circuit is in the range of 24 mA per output and the greater the number of outputs switching simultaneously, the larger will be the ground bounce.
Similarly, the noise associated with pull-up transistors causes current surges and voltage transients on the power supply lines due to the L * di/dt voltage drop across the Vcc bonding wire.
FIG. 2 depicts ground bounce noise during the switching of an output signal from high to low, and its effect on the output signal.
FIG. 3 is a prior art output buffer circuit 300. Output buffer 300 is enabled when output enable signal oenb is high. When enabled, output buffer 300 is non-inverting and buffers the data received on input lead 301 to drive the capacitive load coupled to output lead 351. When the input data is a logic one, input circuit 380 (which includes N channel transistors 312 and 313, and P channel transistor 311) drives both en.sub.-- top.sub.-- and en.sub.-- bot signals low. This is accomplished by P channel pull-up transistor 311 turning off and N channel pull-down transistor 313 turning on, which pulls down the en.sub.-- hot signal and, through turned on N channel transistor 312, pulls down the en.sub.-- top.sub.-- signal. With the en.sub.-- top.sub.-- signal low, the pull-up transistor chain, consisting of P channel transistor 317 and NPN transistor 341, is enabled and N channel transistors 318 and 319 are disabled. This provides base drive to NPN pull-up transistor 342, and with a low en.sub.-- top.sub.-- signal, N channel transistor 320 is off. With the en.sub.-- bot signal low, N channel pull-down path transistors 321 and 322 are turned off, and N channel transistor 323, driven by inverter 332, is turned on, keeping NPN pull-down transistor 343 turned off. Hence, bipolar transistors 341 and 342 are on and bipolar transistor 343 is off, causing output lead 351 to be pulled up to VCC - 2 Vbe, where Vbe is the base-emitter forward voltage (typically about 0.8 v) of NPN transistors 341 and 342, with no voltage drop across P channel transistor 317.
Conversely, when the input data is a logic zero, signals en.sub.-- top.sub.-- and en.sub.-- bot are driven high by input circuit 380, with P channel pull-up transistor 311 turned on to pull up the en.sub.-- top.sub.-- signal, and via turned on N channel transistor 312, pulling up the en.sub.-- bot signal. This causes the pull-down path established by the emitter-collector path of NPN pull-down transistor 343 established by the collector-emitter path of NPN pull-up transistor 342 to be enabled and the pull-up path established by the collector-emitter path of NPN pull-up transistor 342 to be disabled. This causes output lead 351 to be pulled low, to VSS (ground).
Output buffer 380 does not have any ability to control ground bounce that is generated when output lead 351 is discharged to VSS through the pull-down path of transistors 321, 322, and 343. Hence, this creates an undesirable situation that can cause a system problem.
A number of prior art output circuits which attempt to reduce the effects of ground bounce are known. U.S. Pat. No. 5,296,758 to Sandhu includes compensating devices positioned between the input line and the gate of the pull-down transistor to regulate drive current to the pull-down transistor in the presence of ground bounce. Other prior art circuits, such as described in U.S. Pat. No. 4,959,565 to Knecht et. al., include a plurality of pull-up transistors connected in parallel and/or a plurality of pull-down transistors connected in parallel, whose turn on are distributed in time, in order to reduce the effects of ground bounce. However, such prior art circuits are not completely effective in removing the effects of ground bounce and are not responsive to the effects of ground bounce itself during their operation to attempt to control the effects of ground bounce.